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dma.h
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1 
16 enum dma_mode_bit_t {
17  DMA_MODE_DEMAND = 0x00,
18  DMA_MODE_SINGLE = 0x40,
19  DMA_MODE_BLOCK = 0x80,
20  DMA_MODE_CASCADE = 0xC0,
21 
22  DMA_MODE_ADDR_DEC = 0x20,
24  DMA_MODE_AUTO_INIT = 0x10,
25 
26  DMA_MODE_TX_VERYFY = 0x00,
27  DMA_MODE_TX_WRITE = 0x04,
29  DMA_MODE_TX_READ = 0x08,
31  DMA_MODE_TX_ILLEGAL = 0x0C,
32 };
33 
34 enum dma_channel_t {
35  DMA_CH0 = 0x00,
36  DMA_CH1 = 0x01,
37  DMA_CH2 = 0x02,
38  DMA_CH3 = 0x03,
39 
40  DMA_8BIT = 0x00,
41  DMA_16BIT = 0x01,
42 
43  DMA_MAX_TYPE = 0x02,
44  DMA_MAX_CHANNEL = 0x08,
45 };
46 
51 enum dma_mask_bit_t {
52  /* Set/Clear mask bit 2 */
53  DMA_MASK_DISABLE_CH = 0x04,
54 };
55 
56 struct dma_port_entry_t {
57  unsigned char page;
58  unsigned char address;
59  unsigned char count;
60 };
61 
62 struct dma_ctrl_port_entry_t {
63  unsigned char status;
64  unsigned char command;
65  unsigned char request;
66  unsigned char single_mask;
67  unsigned char write_mode;
68  unsigned char byte_ptr;
69  unsigned char intermediate;
70  unsigned char dma_mask;
71 };
72 
82 extern void dma_init(int ch, int mode, unsigned long address, int count);
83 
90 extern int dma_is_done(int ch);
91 
98 extern struct dma_ctrl_port_entry_t *dma_get_ctrl_port(int type);
99 
106 extern struct dma_port_entry_t *dma_get_port(int channel);
107