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fdc.h
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1 
13 enum {
14  FD_SECTOR_PER_TRACK = 18,
15  FD_HEAD = 2,
16  FD_BLKSZ = 512,
17 };
18 
19 /* 0x3F0 ~ 0x3F7 */
23 enum base_address {
24  FDC_PRIMARY = 0x3F0,
25  FDC_SECONDARY = 0x370,
26  FDC_BASE_MAX = 0xFFFF,
27 };
28 
30 enum bytes_per_sector {
31  SECTOR_128 = 0,
32  SECTOR_256 = 1,
33  SECTOR_512 = 2,
34  SECTOR_1024 = 3,
35 };
36 
37 /* IDX:0, R - SRA */
38 #define REG_SRA(base) (base)
39 #define SRA(reg) ((SRA_t*)(ret))
40 
41 typedef struct status_register SRA_t;
42 struct status_register {
43 #if defined(MODE_PS2)
44  unsigned long dir:1;
45  unsigned long b_wp:1;
46  unsigned long b_idx:1;
47  unsigned long hdsel:1;
48  unsigned long b_trk0:1;
49  unsigned long step:1;
50  unsigned long b_drv2:1;
51  unsigned long interrupted:1;
52 #define SRA_RESET_DONE(reg) (!SRA(reg)->interrupted && !SRA(reg)->step && !SRA(reg)->hdsel && !SRA(reg)->dir)
53 #define SRA_INTERRUPTED(reg) (SRA(reg)->interrupted)
54 
55 #elif defined(MODE_MODEL30)
56  unsigned long b_dir:1;
57  unsigned long wp:1;
58  unsigned long index:1;
59  unsigned long b_hdsel:1;
60  unsigned long trk0:1;
61  unsigned long step_ff:1;
62  unsigned long drq:1; /* DMA Request */
63  unsigned long interrupted:1;
64 
65 #define SRA_RESET_DONE(reg) (!SRA(reg)->step_ff)
66 #define SRA_INTERRUPTED(reg) (((SRA_t*)(reg))->interrupted)
67 
68 #elif defined(MODE_PCAT)
69  unsigned char none;
70 #define SRA_RESET_DONE(reg) 1
71 #define SRA_INTERRUPTED(reg) 0
72 #endif
73 };
74 
75 /* IDX:1, R - SRB */
76 #define REG_SRB(base) ((base) + 0x01)
77 #define SRB(reg) ((SRB_t*)(reg))
78 typedef struct status_register_b SRB_t;
79 struct status_register_b {
80 #if defined(MODE_PS2)
81  unsigned long motor:2;
82  unsigned long we:1;
83  unsigned long rddata_toggle:1;
84  unsigned long wrdata_toggle:1;
85  unsigned long drive_sel0:1;
86  unsigned long reserved:2; /* 11 */
87 #define SRB_RESET_DONE(reg) (!SRB(reg)->rddata_toggle && !SRB(reg)->wrdata_toggle)
88 #elif defined(MODE_MODEL30)
89  unsigned long b_ds_high:2;
90  unsigned long we_ff:1;
91  unsigned long rddata_ff:1;
92  unsigned long wrdata_ff:1;
93  unsigned long b_ds_low:2;
94  unsigned long b_drv2:1;
95 #define SRB_RESET_DONE(reg) (!SRB(reg)->we_ff && !SRB(reg)->rddata_ff && !SRB(reg)->wrdata_ff)
96 #elif defined(MODE_PCAT)
97  unsigned char none;
98 #define SRB_RESET_DONE(reg) 1
99 #endif
100 };
101 
102 /* IDX2, RW - DOR */
103 #define REG_DOR(base) ((base) + 0x02)
104 enum drive_activation_values {
105  DRIVE0 = 0x1C,
106  DRIVE1 = 0x2D,
107  DRIVE2 = 0x4E,
108  DRIVE3 = 0x8F,
109 };
110 
111 typedef struct digital_output_register DOR_t;
112 struct digital_output_register {
113  unsigned long drive:2;
114  unsigned long b_reset:1;
115  unsigned long b_dma_gate:1;
116  unsigned long motor:4;
117 };
118 
119 enum dma_state {
120  DMA = 0x01,
121  NONDMA = 0x00,
122 };
123 
124 #define DOR_RESET(ctx) \
125 do { \
126  unsigned reg; \
127  DOR_t *dor = (DOR_t*)® \
128  dor->b_reset = 0; \
129  dor->drive = 0; \
130  dor->b_dma_gate = 0; \
131  dor->motor = 0; \
132  outb(REG_DOR((ctx)->ctrl), reg); \
133 } while (0)
134 
135 #define DOR_ENABLE(ctx, drv, dma) \
136 do { \
137  unsigned char reg; \
138  DOR_t *dor = (DOR_t*)® \
139  dor->b_reset = 1; \
140  dor->drive = (drv); \
141  dor->b_dma_gate = (dma); \
142  dor->motor = 0x01 << (drv); \
143  outb(REG_DOR((ctx)->ctrl), reg); \
144 } while (0)
145 
146 /* IDX:3, RW - TDR */
147 #define REG_TDR(base) ((base) + 0x03)
148 typedef struct tape_drive_register TDR_t;
149 struct tape_drive_register {
150  unsigned long tape_sel:2;
151  unsigned long none:6;
152 };
153 
154 /* IDX:4, W - DSR */
155 #define REG_DSR(base) ((base) + 0x04)
156 enum precompensation_delays {
157  DELAY_DISABLED = 0x07,
158  DELAY_41_67ns = 0x01, /* 1Mbps */
159  DELAY_83_34ns = 0x02,
160  DELAY_125ns = 0x03, /* 500Kbps, 300Kbps, 250Kbps */
161  DELAY_166_67ns = 0x04,
162  DELAY_208_33ns = 0x05,
163  DELAY_250ns = 0x06,
164  DELAY_DEFAULT = 0x0,
165 };
166 
167 enum data_rates {
168  DRATE_1Mbps = 0x03, /* 41.67ns */
169  DRATE_500Kbps = 0x00, /* 125ns */
170  DRATE_300Kbps = 0x01, /* 125ns */
171  DRATE_250Kbps = 0x02, /* 125ns */
172 };
173 
174 typedef struct datarate_select_register DSR_t;
175 struct datarate_select_register {
176  unsigned long dratesel:2;
177  unsigned long precomp:3;
178  unsigned long zeroed:1;
179  unsigned long power_down:1;
180  unsigned long sw_reset:1;
181 };
182 
183 #define SELECT_DRATE(reg, rate) \
184 do { \
185  DSR_t *dsr = (DSR_t*)(reg); \
186  dsr->dratesel = rate; \
187  switch (dsr->dratesel) { \
188  case DRATE_1Mbps: \
189  dsr->precomp = DELAY_41_67ns; \
190  break; \
191  case DRATE_500Kbps: \
192  dsr->precomp = DELAY_125ns; \
193  break; \
194  case DRATE_300Kbps: \
195  dsr->precomp = DELAY_125ns; \
196  break; \
197  case DRATE_250Kbps: \
198  dsr->precomp = DELAY_125ns; \
199  break; \
200  default: \
201  break; \
202  } \
203 } while (0)
204 
205 /* Auto-toggle reset_pin */
206 #define DSR_RESET(reg) \
207 do { \
208  DSR_t *dsr = (DSR_t*)(reg); \
209  dsr->sw_reset = 1; \
210  dsr->power_down = 1; \
211 } while (0)
212 
213 /* IDX:4, R - MSR */
214 #define REG_MSR(base) ((base) + 0x04)
215 enum drive_letter {
216  DRIVE_A = 0x00,
217  DRIVE_B = 0x01,
218  DRIVE_C = 0x02,
219  DRIVE_D = 0x03,
220  DRIVE_MAX = 0xFF,
221 };
222 
223 enum dir_of_data {
224  UNDEFINED = 0x00,
225  READ_REQUIRED = 0x01,
226  WRITE_REQUIRED = 0x02,
227  MAX_DIR_OF_DATA = 0xFF,
228 };
229 
230 typedef struct main_status_register MSR_t;
231 struct main_status_register {
232  unsigned long drive_busy:4;
233  unsigned long cmd_busy:1;
234  unsigned long non_dma:1; /* 1 = during execution phase */
235  unsigned long DIO:1; /* 1 = read is required, otherwise(0) write is required */
236  unsigned long RQM:1; /* 1 = host can transfer data, otherwise 0 */
237 };
238 
239 #define MSR(reg) ((MSR_t*)(reg))
240 #define DIR_OF_DATA(reg) (MSR(reg)->RQM ? (MSR(reg)->DIO ? READ_REQUIRED : WRITE_REQUIRED) : UNDEFINED)
241 #define IN_RESULT_PHASE(reg) (MSR(reg)->cmd_busy)
242 #define IN_SEEK_PORTION(reg) (MSR(reg)->drive_busy)
243 
244 #define REG_FIFO(base) ((base) + 0x05)
245 /* IDX:5, RW - FIFO */
246 /* NO DATA STRUCTURE */
247 
248 /* IDX:6, RESERVED */
249 
250 /* IDX:7, R - DIR */
251 #define REG_DIR(base) ((base) + 0x07)
252 typedef struct digital_input_register DIR_t;
253 struct digital_input_register {
254 #if defined(MODE_PCAT)
255  unsigned long none:7;
256  unsigned long disk_change:1;
257 #define DISK_CHANGED(reg) (((DIR_t*)(reg))->disk_change)
258 #elif defined(MODE_PS2)
259  unsigned long b_high_dens:1; /* 500Kbps, 1Mbps -> set 1 */
260  unsigned long drate_sel:2;
261  unsigned long reserved:4; /* set 1 */
262  unsigned long disk_change:1;
263 #define DISK_CHANGED(reg) (((DIR_t*)(reg))->disk_change)
264 #elif defined(MODE_MODEL30)
265  unsigned long drate_sel:2;
266  unsigned long no_prec:1;
267  unsigned long b_dma_gate:1;
268  unsigned long reserved:3; /* set 0 */
269  unsigned long b_disk_change:1;
270 #define DISK_CHANGED(reg) (!((DIR_t*)(reg))->disk_change)
271 #else
272  unsigned char none;
273 #endif
274 };
275 
276 /* IDX:7, W -CCR */
277 #define REG_CCR(base) ((base) + 0x07)
278 typedef struct configuration_control_register CCR_t;
279 struct configuration_control_register {
280 #if defined(MODE_PCAT) || defined(MODE_PS2)
281  unsigned long drate_sel:2;
282  unsigned long none:6;
283 #elif defined(MODE_MODEL30)
284  unsigned long drate_sel:2;
285  unsigned long no_prec:1;
286  unsigned long none:5;
287 #endif
288 };
289 
290 #define SET_DRATE(reg, drate) (((CCR_t*)(reg))->drate_sel = (drate))
291 
292 enum fdc_dma_dir_t {
293  FDC_DMA_READ = 1,
294  FDC_DMA_WRITE = 2,
295 };
296 
297 enum command_set {
298  CMD_READ_DATA = 0x06,
299  CMD_READ_DELETED_DATA = 0x0C,
300  CMD_WRITE_DATA = 0x05,
301  CMD_WRITE_DELETED_DATA = 0x09,
302  CMD_READ_TRACK = 0x02,
303  CMD_VERIFY = 0x16,
304  CMD_VERSION = 0x10,
305  CMD_FORMAT_TRACK = 0x0D,
306  CMD_SCAN_EQUAL = 0x11,
307  CMD_SCAN_LOW_OR_EQUAL = 0x19,
308  CMD_SCAN_HIGH_OR_EQUAL = 0x1D,
309  CMD_RECALIBRATE = 0x07,
310  CMD_SENSE_INTERRUPT = 0x08,
311  CMD_SPECIFY = 0x03,
312  CMD_SEND_DRIVE_STATUS = 0x04,
313  CMD_SEEK = 0x0F,
314  CMD_CONFIGURE = 0x13,
315  CMD_RELATIVE_SEEK = 0x8F,
316  CMD_DUMPREG = 0x0E,
317  CMD_READ_ID = 0x0A,
318  CMD_PERPENDICULAR_MODE = 0x12,
319  CMD_LOCK = 0x14,
320 
321  CMD_EXT_MULTITRACK = 0x80,
322  CMD_EXT_DENSITY = 0x40,
323  CMD_EXT_SKIP = 0x20,
324 };
325 
326 enum symbol {
327  EIS = 0x06,
328  EFIFO = 0x05,
329  POLL = 0x04,
330 };
331 
332 /*
333  * 1 ~ 18 = 0 0
334  * 19 ~37 = 1 1
335  * 38 ~56 = 0 2
336  */
337 
342 #define LBA_TO_CHS(lba, h, t, s) \
343 do { \
344  (h) = ((lba) % (FD_SECTOR_PER_TRACK * FD_HEAD)) / FD_SECTOR_PER_TRACK; \
345  (t) = (lba) / (FD_SECTOR_PER_TRACK * FD_HEAD); \
346  (s) = ((lba) % FD_SECTOR_PER_TRACK) + 1; \
347 } while (0)
348 
349 #define VALIDATE_RESULT(ctx) do { \
350  int ret; \
351  unsigned char byte; \
352  ret = read_byte(ctx, &byte); \
353  if (ret < 0 || byte == 0x80) \
354  printf("Failed to read\n"); \
355 } while (0)
356 
357 struct fdc_context {
358  enum base_address ctrl;
359  enum drive_letter drv;
360  sem_t sem;
361 };
362 
363 extern int fdc_init(void);
364 
365 /* \} */